In recent years, increasing numbers of electronic products use flash memory devices for data storage. These flash memory devices store configuration data, operating system programs, multi-media data, etc. These flash memory devices need to be configured or programmed before they can be used in an electronic product. One of the issues in manufacturing is the programming of the flash memory devices, because of time utilized in programming the large amount of data to be stored in the flash memory devices. This issue becomes worse as the storage density of the flash memory devices increases in each newer generation.
To program the flash memory devices, a manufacturer has three options. The first option is to pre-program the flash memory devices before inserting them into a printed circuit (PC) board. However, this approach increases the cost of manufacturing because it requires extra fixtures to program the flash memory devices, and the flash memory devices once programmed cannot be used for other purposes.
The second option is to program the flash memory devices after they have been installed on the PC board. One way to accomplish such an in-system programming (ISP) is to first install a small program into a microprocessor, and then have the microprocessor program the flash memory device from an external data source, such as a manufacturing test system.
A detailed description of ISP is found in “IEEE Standard for In-System Configuration of Programmable Devices,” (a.k.a. IEEE Standard 1532-2002) published by Test Technical Council of the IEEE Computer Society on Dec. 11, 2002. However, this method also requires extra manufacturing fixtures and the data transfer to the flash memory device is inefficient.
A third way of performing in-system programming is to use Joint Test Action Group (JTAG) scan chain to control the pins which are connected to the flash memory. A detailed description of the JTAG test methodology is found in “IEEE Standard Test Access Port and Boundary-Scan Architecture,” (a.k.a. IEEE Standard 1149.1-2001) published by Test Technology Standards committee of the IEEE Computer Society on Jun. 14, 2001. FIG. 1 illustrates an existing method for programming a flash memory device by using a JTAG scan chain. As shown in FIG. 1, a PC board 100 includes a programmable logic device (“PLD”) 102. The PLD 102 works with many devices on the PC board, for example, a microprocessor 104, an application specific integrated circuit (ASIC) 106, a FPGA 108, display LEDs 110, a static random access memory (SRAM) 112, a system bus 114, a JTAG scan chain 116, a JTAG boundary scan chain 117, which bounds the PLD 102, and a flash memory device 118.
In many applications, the JTAG boundary scan chain 117 may contain hundreds of pins. However, only a small fraction of these pins connect the PLD 102 to the flash memory 118, as shown by the shaded area 120. This method requires shifting hundreds of bits of data through the entire JTAG boundary scan chain 117 in order to write a few bits of data to the flash memory device 118. Thus, the existing method of using the JTAG boundary scan chain 117 for programming the flash memory device 118 is inefficient.
Additionally, writing bits of data to the flash memory device 118 (i.e., programming the device) through the JTAG boundary scan chain 117 requires the PLD 102 to enter a programming mode, which results in the core of the PLD 102 and other devices connected to the PLD 102 to temporarily cease functioning.
Therefore, there is a need for a method and system that can use JTAG to access a target device through a PLD.